Reduced Instruction Set Computer (RISC) processors are well known. RISC processors have instructions that facilitate the use of a technique known as pipelining. Pipelining enables a processor to work on different steps of an instruction at the same time and thereby take advantage of parallelism that exists among the steps needed to execute an instruction. As a result, a processor can execute more instructions in a shorter period of time. Additionally, modern Complex Instruction Set Computer (CISC) processors often translate their instructions into micro-operations (i.e., instructions similar to those of a RISC processor) prior to execution to facilitate pipelining.
Many pipelined processors, especially those used in the embedded market, are relatively simple single-threaded in-order machines. As a result, they are subject to control, structural, and data hazard stalls. More complex processors are typically multi-threaded processors that have out-of-order execution pipelines. These more complex processors schedule execution of instructions around hazards that would stall an in-order machine.
A conventional multi-threaded out-of-order processor has multiple dedicated buffers that are used to reorder instructions executed out-of-order so that each instruction graduates (i.e., writes its result to a general purpose register file and/or other memory) in program order. For example, a conventional N-threaded out-of-order processor has N dedicated buffers for ensuring instructions graduate in program order; one buffer for each thread that can be run on the processor. A shortcoming of this approach, for example, is that it requires a significant amount of integrated circuit chip area to implement N separate buffers. This approach can also degrade performance in some designs when only a single program thread is running on a multi-threaded processor, for example, if each of the N buffers is limited in size in order to reduce the overall area of the N buffers.
What is needed is a processor that overcomes the limitations noted above.